Multi-Core and Many-Core systems for EMbedded Computing (MC)3

Recent trends in the microprocessor industry have important ramifications for the design of the next generation of embedded computing systems. By increasing number of cores, it is possible to improve the performance while keeping the power consumption unchanged. This trend has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers. It is also expected that the number of cores in these systems rises dramatically in the near future.

Although these systems can potentially provide significant performance benefits, in practice, there are technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. Therefore, it is necessary to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.

This special session addresses all aspects of multi-core and many-core embedded systems design. It presents new ideas in the multi-core field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, algorithms, software, tools and applications, analysis and comparison, design techniques and emerging implementations.

Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:

  • Design space exploration and design methodology for embedded multi-core and many-core systems
  • Specification and Formal modeling of embedded multi-core and many-core systems
  • Multi-core/many-core embedded system design challenges
  • Parallel programming and software for embedded multi-core and many-core systems
  • Memory management
  • 3D architectures, integration and synthesis for embedded multi-core and many-core systems
  • On-chip communication architectures and networks-on-chip for embedded systems
  • Heterogeneous multi-core and many-core architectures
  • Hardware/software co-design
  • Simulation, validation and verification
  • QoS management and performance analysis
  • Multi-core and many-core cyber-physical systems
  • Programming languages and compilers
  • Thermal-, energy-, and power-aware architectures
  • Monitoring and reconfiguration
  • System prototyping
  • Industrial practices and case studies

Important dates

Paper submission: 31st Aug 2013
Acceptance notification: 7th Oct 2013 21st Oct 2013
Camera ready due: 31st Oct 2013 21st Nov 2013
Conference: 12th - 14th Feb 2014


  • Amir-Mohammad Rahmani, University of Turku, Finland
  • Pasi Liljeberg, University of Turku, Finland
  • Juha Plosila, University of Turku, Finland

Programme Committee:

  • Hannu Tenhunen, Royal Institute of Technology, Sweden
  • José L. Ayala, Complutense University of Madrid, Spain
  • Waltenegus Dargie, Technical University of Dresden, Germany
  • Thomas Hollstein, Tallinn University of Technology, Estonia
  • Zhonghai Lu, Royal Institute of Technology, Sweden
  • Jari Nurmi, Tampere University of Technology, Finland
  • Leandro Soares Indrusiak, University of York, UK
  • Jouni Isoaho, University of Turku, Finland
  • Dinesh Pamunuwa, Bristol University, UK
  • Mohamed Bakhouya, Aalto University, Finland
  • Sébastien Lafond, Åbo Akademi, Finland
  • Seppo Virtanen, University of Turku, Finland
  • Haoyuan Ying, Darmstadt University of Technology, Germany
  • Leonidas Tsiopoulos, Åbo Akademi, Finland
  • Tiberiu Seceleanu, ABB Corporate Research, Sweden
  • Tomi Westerlund, University of Turku, Finland
  • Gert Jervan, Tallinn University of Technology, Estonia
  • Ye Lu, Queen's University of Belfast, UK
  • Ville Leppänen, University of Turku, Finland
  • Ali Afzali-Kusha, University of Tehran, Iran
  • Shashi Kumar, Jönköping University, Sweden
  • Ethiopia Nigussie, University of Turku, Finland
  • Siamak Mohammadi, University of Tehran, Iran
  • Gabriel Marchesan Almeida, Karlsruhe University, Germany
  • Liang Guang, University of Turku, Finland
  • Ka Lok Man, Xi'an Jiaotong-Liverpool University, China and Myongji University, South Korea and Baltic Institute of Advanced Technology, Lithuania
  • Jerker Björkqvist, Åbo Akademi, Finland

Submission guidelines

Prospective authors should submit a full paper not exceeding 8 pages in the IEEE Conference proceedings format (IEEEtran, double-column, 10pt). Double-bind review: the first page of the paper should contain only the title and abstract; in the reference list, references to the authors' own work should appear as "omitted for blind review" entries. Manuscript submission


Proceedings will be published by the Conference Publishing Services (CPS) in the same volume of the main track. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted for inclusion in Xplore and the CSDL, and for indexing, among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.

Authors of selected papers will be invited to submit extended article versions to one of the ISI-indexed high-quality journals.


Amir-Mohammad Rahmani
Department of Information Technology
University of Turku, Finland
E-mail: amir(-dot-)rahmani(-at-)utu(-dot-)fi
Tel: (+358) 443-462629